Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - SDRAM controller verilog

Search list

[Other resource] mem_ctrl.tar

Description: verilog 写的 memory controller ，可以控制SDRAM SRAM NOR
Platform: | Size: 331413 | Author: youjia | Hits:

[VHDL-FPGA-Verilog] DE2_LCM_CCD

Description: 在de2FPGA开发板上实现视频的采集，以及播放~~verilog代码 希望对大家有所帮助-CCD to capture video sent to SDRAM LCM to controller LCD LCD to display the picture~
Platform: | Size: 4648960 | Author: Wu | Hits:

[VHDL-FPGA-Verilog] sdr_verilog

Description: 用Verilog实现SDR_SDRAM的控制器,可用FPGA实现对普通SDRAM的读写操作!-SDR_SDRAM using Verilog implementation of the controller, the FPGA can be used to achieve the ordinary SDRAM read and write operations!
Platform: | Size: 37888 | Author: 许文建 | Hits:

[VHDL-FPGA-Verilog] sdram_control

Description: 基于硬件语言Verilog的一个sdram控制器的设计以及仿真-Verilog language, a hardware-based controller design and simulation sdram
Platform: | Size: 2784256 | Author: 林不野 | Hits:

[VHDL-FPGA-Verilog] Sdram_Control_4Port

Description: 使用verilog HDL写的sdram(SDR)的控制器源代码，具有很好的可移植性，试验的例子已经通过QuartusII 9.0编译通过，可以运行在cycloneII上-Controller source code using verilog HDL written in the sdram (SDR), has good portability, test examples via the QuartusII 9.0 compiler, you can run in cycloneII
Platform: | Size: 20480 | Author: 李立鸣 | Hits:

[VHDL-FPGA-Verilog] dab1814114c3

Description: 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Description ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the verilog testbench, modelsim project file, and library \source Contains the verilog source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 880640 | Author: 李志偉 | Hits:

[VHDL-FPGA-Verilog] verilogsram

Description: 一个基于verilog的sdram读写控制器，可以将数据写入sdram并读回。-One based on the sdram verilog write controller, data can be written to and read back sdram.
Platform: | Size: 96256 | Author: 陈栋磊 | Hits:

[Other Embeded program] testsdram

Description: 一个用Verilog语言编写的SDRAM控制器源码, 逻辑清晰, 结构合理!-SDRAM controller is a source code in Verilog language, logical, reasonable structure!
Platform: | Size: 462848 | Author: yzhq | Hits:

[VHDL-FPGA-Verilog] wb_sdram_ctrl.tar

Description: Generic Wishbone R3 compliant SDRAM controller written in Verilog
Platform: | Size: 10240 | Author: corgano | Hits:

[VHDL-FPGA-Verilog] 5_Gray_Mean_Filter

Description: 均值滤波是典型的线性滤波算法，（Verilog HDL）设计所需的模块有： （1）带PLL的全局时钟管理模块 system_ctrl_pll.v （2）OV7725 COMS Sensor的初始化模块 i2c_timing_ctrl、I2C_OV7725_RGB565_Conofig （3）OV7725 COMS Sensor的视频信号采集模块COMS_Capture_RGB565 （4）SDRAM数据交互控制器Sdram_Control_2Port （5）VGA时序驱动电路lcd_driver -Design the required modules are: (1) global with PLL clock management module system_ctrl_pll. V. (2) the OV7725 COMS i2c_timing_ctrl initialization module, I2C_OV7725_RGB565_Conofig Sensor (3) the OV7725 COMS Sensor COMS_Capture_RGB565 video signal acquisition module (4) SDRAM controller data interaction Sdram_Control_2Port (5) the VGA timing drive circuit lcd_driver 逐句翻译
Platform: | Size: 8895488 | Author: Keyonwho | Hits:

[VHDL-FPGA-Verilog] verilog-SDRAM

Description: 用verilog语言写的SDRAM读写控制器的程序，经测试有效。-Written in verilog language SDRAM read and write controller procedures, the test is valid.
Platform: | Size: 21216256 | Author: 谢嘉树 | Hits:
« 1 2 3 4 5 6»

CodeBus www.codebus.net